1. Field of the Invention
This invention relates to power supply monitoring schemes and, more particularly, to a circuit and method for monitoring the integrity of a power supply by monitoring a level of the power supply and/or an electrical connection between the power supply and a power supply pin.
2. Description of the Related Art
The following descriptions and examples are given as background only.
Many integrated circuits and systems, such as microprocessors, microcontrollers and other programmable logic devices, are sensitive to the output levels of the power supplies driving the systems. In fact, such systems are often characterized by unique requirements for initialization control sequences, power-up and power-down control sequences, and unintentional reset sequences that may occur, e.g., during power glitches.
For instance, many programmable logic devices (PLDs) must be “powered-up” or awakened from a zero power state to a point at which the power supply voltage reaches an acceptable operating voltage level. For example, internal memory cells, registers and configuration state machines of the device may all be initialized according to specific power-up reset sequences. Once the power supply voltage reaches an acceptable operating voltage level, the configuration state machine may take control of the configuration process by loading configuration data into volatile memory cells. When all of the data has been loaded, the I/O pins of the PLD are enabled and the device is ready to begin performing its programmed function.
Another reset process takes place when a device is powered down, i.e., when the power supply voltage is brought down from the operating voltage level to the zero power state (or below a triggering voltage level). During the power-down reset sequence, the PLD may detect that the power supply voltage has reached or is nearing an unacceptably low level. If detected, the PLD performs a sequence of operations such as saving current memory cell, register and state machine information, informing other integrated circuits to stop sending data to the PLD, and so forth.
The power-up and power-down reset procedures are complicated by the fact that power supplies can be noisy, sometimes glitching significantly above and/or below a triggering voltage level. For example, assume that the PLD (or another power-dependent component) is included within a computer system that shares a power supply line with various appliances (such as an air conditioner, electric drill, etc.). In some cases, a large current spike may be introduced into the shared supply line when one or more of the appliances are turned on. If the current spike causes the supply line voltage to drop below the acceptable operating voltage level, the PLD may lose volatile information (such as register and memory content) or may enter the wrong configuration state. In addition to glitches, other types of power failure (such as temporary loss of power) may produce the same results by not giving the PLD enough time to perform a proper power-down sequence.
During the power-up reset sequence, a reset signal is typically asserted (i.e., “ON”) when the power supply voltage is rising towards the acceptable operating voltage level, and deasserted (i.e., “OFF”) once the power supply voltages reaches the acceptable level. The power-down reset sequence is similar; however, the reset signal is asserted once the power supply voltage falls below an unacceptable operating voltage level, and deasserted once the power supply voltage reaches the zero power state. To operate properly, both reset sequences must be asserted for a specific duration of time needed to perform the power-up or power-down sequence of operations.
Most conventional systems include at least one power-on reset (POR) circuit for monitoring the power supply voltage and generating a reset signal, in accordance with a power-up and/or power-down reset operation. The POR circuit may also be implemented to ensure that the reset signals are asserted for the required duration. Most POR circuits are based on circuits comprising resistors and capacitors (e.g., RC POR circuits) or, in some cases, voltage comparators comprising voltage dividers and voltage reference generators (e.g., bandgap POR circuits). All provide an active high (or active low) reset signal to one or more system components, indicating that they should perform the necessary power-up or power-down reset functions. However, none of the conventional POR circuits provide indication as to the cause behind the reset signal, thus, leaving the circuit designer or user in the dark as to the reason for the power failure.
For at least these reasons, a need remains for an improved circuit and method for monitoring the integrity of a power supply, where such method provides the circuit designer/user with additional resources/information for diagnosing a cause behind the reset signal, and thus, a reason for the power failure.